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| ltc4278 1 4278fc ? ? ? ? 12m 1f 30.9 24k 1.8k 38.3k 100k 12k 0.1f 33pf 0.1f 2.2nf 1f t on sync pgdly uvlo pwrgd sense ? v cmp sense + r cmp v neg r class shdn v portp v portn endly osc ltc4278 gnd fb v cc sg pg c cmp to micro controller ? 47f 0.18h 5v 4.5a 100f + + 3.01k 21.5k t2p 46.4k 294k 10f 10f 8.2h epc3472g-lf fdms2572 hat2169 54v from data pair auxiliary supply (10v to 57v) 54v from spare pair + ? + ? ~ ~ 4278 ta01a bss63 pds5100h b1100 + ? ~ ~ typical application features applications description ieee 802.3at pd with synchronous no-opto flyback controller and 12v aux support the ltc ? 4278 is an integrated powered device (pd) con - troller and switching regulator intended for high power ieee 802.3at and 802.3af applications. with a wide input voltage range, the ltc4278 is specifcally designed to sup - port pd applications that include a low-voltage auxiliary power input such as a 12v wall adaptor. the inclusion of a shutdown pin provides simple implementation of both poe and auxiliary dominate applications. in addition, the ltc4278 supports both 1-event and 2-event classifcations as defned by the ieee, thereby allowing the use in a wide range of product confgurations. the ltc4278 synchronous, current mode, fyback control - ler generates multiple supply rails in a single conversion step providing for the highest system effciency while main - taining tight regulation across all outputs. the ltc4278 includes linear technologys patented no-opto feedback topology to provide full ieee 802.3 isolation without the need of an opto-isolator circuit. a true soft-start function allows graceful ramp-up of all output voltages. the ltc4278 is available in a space saving 32-lead dfn package. n 25.5w ieee 802.3at compliant (type 2) pd n 10v to 57v auxiliary power input n shutdown pin for flexible auxiliary power support n integrated state-of-the-art no-opto synchronous flyback controller C isolated power supply effciency >92% C 88% effciency including diode bridge and hot swap? fet n superior emi performance n robust 100v 0.7 (typ) integrated hot swap mosfet n ieee 802.3at high power available indicator n integrated signature resistor and programmable class current n undervoltage, overvoltage and thermal protection n short-circuit protection with auto-restart n programmable soft-start and switching frequency n complementary power good indicators n thermally enhanced 7mm 4mm dfn package n voip phones with advanced display options n dual-radio wireless access points n ptz security cameras n rfid readers n industrial controls 25w pd solution with 12v auxiliary l , lt, ltc, ltm, linear technology, switchercad and the linear logo are registered trademarks and hot swap and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5841643.
ltc4278 2 4278fc pin configuration absolute maximum ratings pins with respect to v portn v portp voltage ......................................... C0.3v to 100v v neg voltage ......................................... C0.3v to v portp v neg pull-up current .................................................. 1a shdn ....................................................... C0.3v to 100v r class , voltage ............................................ C0.3v to 7v r class source current ........................................... 50ma pwrgd voltage (note 3) low impedance source ...... v neg C0.3v to v neg +11v sink current ......................................................... 5ma pwrgd , t2p voltage ............................... C0.3v to 100v pwrgd , t2p sink current ..................................... 10ma pins with respect to gnd v cc voltage ................................................ C0.3v to 22v sense C , sense + voltage ........................ C0.5v to +0.5v uvlo, sync voltage ................................... C0.3v to v cc fb current .............................................................. 2ma v cmp current ......................................................... 1ma operating ambient temperature range ltc4278c ................................................ 0c to 70c ltc4278i .............................................. C40c to 85c (notes 1, 2) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v portp nc pwrgd pwrgd nc v neg v neg nc pg pgdly r cmp c cmp sense + sense ? uvlo v cmp shdn t2p r class nc v portn v portn nc nc sg v cc t on endly sync sfst osc fb top view dkd32 package 32-lead (7mm 4mm) plastic dfn t jmax = 125c, ja = 34c/w, jc = 2c/w gnd, exposed pad (pin 33) must be soldered to a heat sinking plane that is connected to v neg order information lead free finish tape and reel part marking* package description temperature range ltc4278cdkd#pbf ltc4278cdkd#trpbf 4278 32-lead (7mm 4mm) plastic dfn 0c to 70c ltc4278idkd#pbf ltc4278idkd#trpbf 4278 32-lead (7mm 4mm) plastic dfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ ltc4278 3 4278fc electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. parameter conditions min typ max units interface controller (note 4) operating input voltage signature range classifcation range on voltage off voltage overvoltage lockout at v portp (note 5) l l l l 1.5 12.5 30.0 71 60 9.8 21 37.2 v v v v v v on/off hysteresis window l 4.1 v signature/class hysteresis window l 1.4 v reset threshold state machine reset for 2-event classifcation l 2.57 5.40 v supply current supply current at 57v measured at v portp pin l 1.35 ma class 0 current v portp = 17.5v, no r class resistor l 0.40 ma signature signature resistance 1.5v v portp 9.8v (note 6) l 23.25 26 k invalid signature resistance, shdn invoked 1.5v v portp 9.8v, v shdn = 3v (note 6) l 11 k invalid signature resistance during mark event (notes 6, 7) l 11 k classifcation class accuracy 10ma < i class < 40ma, 12.5v < v portp < 21v (notes 8, 9) l 3.5 % classifcation stability time v portp pin step to 17.5v, r class = 30.9, i class within 3.5% of ideal value (notes 8, 9) l 1 ms normal operation inrush current v portp = 54v, v neg = 3v l 60 100 180 ma power fet on-resistance tested at 600ma into v neg , v portp = 54v l 0.7 1.0 power fet leakage current at v neg v portp = shdn = v neg = 57v l 1 a digital interface shdn input high level voltage l 3 v shdn input low level voltage l 0.45 v shdn input resistance v portp = 9.8v, shdn = 9.65v l 100 k pwrgd , t2p output low voltage tested at 1ma, v portp = 54v. for t2p, must complete 2-event classifcation to see active low l 0.15 v pwrgd , t2p leakage current pin voltage pulled 57v, v portp = v portn = 0v l 1 a pwrgd output low voltage tested at 0.5ma, v portp = 52v, v neg = 48v, output voltage is with respect to v neg l 0.4 v pwrgd clamp voltage tested at 2ma, v neg = 0v, voltage with respect to v neg l 12 16.5 v pwrgd leakage current v pwrgd = 11v, v neg = 0v, voltage with respect to v neg l 1 a ltc4278 4 4278fc electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. parameter conditions min typ max units pwm controller (note 10) power supply v cc operating range l 4.5 20 v v cc supply current (i cc ) v cmp = open (note 11) l 4 6.4 10 ma v cc shutdown current v cmp = open, v uvlo = 0v l 50 150 a feedback amplifer feedback regulation voltage (v fb ) l 1.220 1.237 1.251 v feedback pin input bias current r cmp open 200 na feedback amplifer transconductance ?i c = 10a l 700 1000 1400 mho feedback amplifer source or sink current l 25 55 90 a feedback amplifer clamp voltage v fb = 0.9v v fb = 1.4v 2.56 0.84 v v reference voltage line regulation 12v v cc 18v l 0.005 0.05 %/ v feedback amplifer voltage gain v cmp = 1.2v to 1.7v 1400 v/ v soft-start charging current v sfst = 1.5v 16 20 25 a soft-start discharge current v sfst = 1.5v, v uvlo = 0v 0.7 1.3 ma control pin threshold (v cmp ) duty cycle = min 1 v gate outputs pg, sg output high level l 6.6 7.4 8 v pg, sg output low level l 0.01 0.05 v pg, sg output shutdown strength v uvlo = 0v; i pg , i sg = 20ma l 1.6 2.3 v pg rise time c pg = 1nf 11 ns sg rise time c sg = 1nf 15 ns pg, sg fall time c pg , c sg = 1nf 10 ns current amplifer switch current limit at maximum v cmp v sense + l 88 98 110 mv ?v sense / ?v cmp 0.07 v/ v sense voltage overcurrent fault voltage v sense + , v sfst < 1v l 206 230 mv timing switching frequency (f osc ) c osc = 100pf l 84 100 110 khz oscillator capacitor value (c osc ) (note 12) 33 200 pf minimum switch on time (t on(min) ) 200 ns flyback enable delay time (t endly ) 265 ns pg turn-on delay time (t pgdly ) 200 ns maximum switch duty cycle l 85 88 % sync pin threshold l 1.53 2.1 v sync pin input resistance 40 k ltc4278 5 4278fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: pins with 100v absolute maximum guaranteed for t 0c, otherwise 90v. note 3: active high pwrgd internal clamp self-regulates to 14v with respect to v neg . note 4: all voltages are with respect to v portn pin unless otherwise noted. note 5: input voltage specifcations are defned with respect to ltc4278 pins and meet ieee 802.3af/at specifcations when the input diode bridge is included. note 6: signature resistance is measured via the ? v/ ?i method with the minimum ? v of 1v. the ltc4278 signature resistance accounts for the additional series resistance in the input diode bridge. note 7: an invalid signature after the 1st classifcation event is mandated by the ieee802.3at standard. see the applications information section. note 8: class accuracy is with respect to the ideal current defned as 1.237/r class and does not include variations in r class resistance. note 9: this parameter is assured by design and wafer level testing. note 10: v cc = 14v; pg, sg open; v cmp = 1.4v, v sense C = 0v, r cmp = 1k, r ton = 90k, r pgdly = 27.4k, r endly = 90k, unless otherwise specifed. all voltages are with respect to gnd. note 11: supply current does not include gate charge current to the mosfets. see the applications information section. note 12: component value range guaranteed by design. electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. parameter conditions min typ max units load compensation load compensation to v sense offset voltage v rcmp with v sense + = 0v 0.8 mv feedback pin load compensation current v sense + = 20mv, v fb = 1.230v 20 a uvlo function uvlo pin threshold (v uvlo ) l 1.215 1.240 1.265 v uvlo pin bias current v uvlo = 1.2v v uvlo = 1.3v C0.25 C4.50 0.1 C3.4 0.25 C2.50 a a ltc4278 6 4278fc signature resistance vs input voltage pwrgd , t2p output low voltage vs current active high pwrgd output low voltage vs current inrush current vs input voltage current (ma) 0 v pwrgd ? v portn (v) v t2p ? v portn (v) 0.4 0.6 8 4278 g07 0.2 0 2 4 6 10 0.8 t a = 25c ! current (ma) 0 0 pwrgd (v) 0.4 1.0 0.5 1 4278 g08 0.2 0.8 0.6 1.5 2 t a = 25c v portp ? v neg = 4v v portp voltage (v) 40 85 current (ma) 115 45 50 4278 g09 55 60 90 100 105 110 95 90 100 105 110 95 class operation vs time on-resistance vs temperature v portp voltage (v) 1 22 v1: v2: signature resistance (k ) 23 25 26 27 3 5 4278 g04 24 7 9 6 10 2 4 8 28 resistance = diodes: hd01 t a = 25c = v i v2 ? v1 i 2 ? i 1 ieee upper limit ieee lower limit ltc4278 only ! ltc4278 + 2 diodes v portp voltage 10v/div class current 10ma/div time (10s/div) 4278 g05 t a = 25c ! junction temperature (c) ?50 0.2 resistance () 0.4 0.6 0.8 1.0 ?25 0 25 50 4278 g06 75 100 typical performance characteristics input current vs input voltage 25k detection range input current vs input voltage input current vs input voltage v portp voltage (v) 0 0 v portp current (ma) 0.1 0.2 0.3 0.4 0.5 2 4 6 8 4278 g01 10 t a = 25c v portp voltage (v) (rising) 0 0 v portp current (ma) 10 20 30 40 50 10 20 30 40 4278 g02 50 60 t a = 25c class 4 class 3 class 2 class 1 class 0 ! v portp voltage (v) 12 9.5 v portp current (ma) 10.5 14 16 4278 g03 10.0 18 20 22 11.0 85c ?40c class 1 operation ! ltc4278 7 4278fc temperature (c) ?50 8 9 25 75 4278 g12 7 6 ?25 0 50 100 125 5 4 3 10 i vcc (ma) dynamic current c pg = 1nf, c sg = 1nf, f osc = 100khz static part current v cc = 14v temperature (c) ?50 90 sense voltage (mv) 92 96 98 100 110 104 0 50 75 4278 g13 94 106 108 102 ?25 25 100 125 fb = 1.1v sense = v sense + with v sense ? = 0v temperature (c) ?50 sense voltage (mv) 215 25 4278 g14 200 190 ?25 0 50 185 180 220 210 205 195 75 100 125 sense = v sense + with v sense ? = 0v temperature (c) ?50 90 f osc (khz) 92 96 98 100 110 104 0 50 75 4278 g15 94 106 108 102 ?25 25 100 125 c osc = 100pf temperature (c) ?50 1.230 v fb (v) 1.231 1.233 1.234 1.235 1.240 1.237 0 50 75 4278 g16 1.232 1.238 1.239 1.236 ?25 25 100 125 temperature (c) ?50 feedback pin input bias (na) 200 250 300 25 75 4278 g17 150 100 ?25 0 50 100 125 50 0 r cmp open temperature (c) ?50 v fb reset (v) 1.03 25 4278 g18 1.00 0.98 ?25 0 50 0.97 0.96 1.04 1.02 1.01 0.99 75 100 125 typical performance characteristics v cc shutdown current vs temperature v cc current vs temperature sense voltage vs temperature sense fault voltage vs temperature oscillator frequency vs temperature v fb vs temperature feedback pin input bias vs temperature v fb reset vs temperature temperature (c) ?50 v cc current (a) 60 80 90 25 75 4278 g02 40 50 70 30 20 ?25 0 50 100 125 10 0 v cc = 14v v uvlo = 0 v fb (v) 0.9 ?70 i vcmp (a) ?50 ?30 ?10 70 30 1 1.1 1.4 50 10 1.2 1.3 1.5 4278 g19 125c 25c ?40c feedback amplifer output current vs v fb ltc4278 8 4278fc temperature (c) ?50 uvlo (v) 1.240 1.245 1.250 25 75 4278 g23 1.235 1.230 ?25 0 50 100 125 1.225 1.220 temperature (c) ?50 3.4 3.5 3.7 25 75 4278 g24 3.3 3.2 ?25 0 50 100 125 3.1 3.0 3.6 i uvlo (a) temperature (c) ?50 sfst charge current (a) 23 25 4278 g25 20 18 ?25 0 50 17 16 15 22 21 19 75 100 125 capacitance (nf) 0 time (ns) 80 70 60 50 40 30 20 10 0 8 4278 g26 2 4 6 10 7 1 3 5 9 t a = 25c fall time rise time typical performance characteristics uvlo vs temperature i uvlo hysteresis vs temperature soft-start charge current vs temperature pg, sg rise and fall times vs load capacitance temperature (c) ?50 i vcmp (a) 60 65 70 25 75 4278 g20 55 50 ?25 0 50 100 125 45 40 source current v fb = 1.1v sink current v fb = 1.4v temperature (c) ?50 900 g m (mho) 950 1000 1050 1100 ?25 0 25 50 4278 g21 75 100 125 feedback amplifer source and sink current vs temperature feedback amplifer g m vs temperature temperature (c) ?50 a v (v/v) 1550 25 4278 g22 1400 1300 ?25 0 50 1250 1200 1150 1100 1600 1650 1700 1500 1450 1350 75 100 125 feedback amplifer voltage gain vs temperature ltc4278 9 4278fc temperature (c) ?50 t on(min) (ns) 330 25 4278 g28 300 280 ?25 0 50 270 260 340 320 310 290 75 100 125 r ton(min) = 158k temperature (c) ?50 0 t pgdly (ns) 50 150 200 250 0 50 75 4278 g29 100 ?25 25 100 125 300 r pgdly = 16.9k r pgdly = 27.4k temperature (c) ?50 t endly (ns) 285 305 325 25 75 4278 g30 265 245 ?25 0 50 100 125 225 205 r endly = 90k minimum pg on-time vs temperature pg delay time vs temperature enable delay time vs temperature typical performance characteristics ltc4278 10 4278fc pin functions shdn (pin 1): shutdown input. use this pin for auxiliary power application. drive shdn high to disable ltc4278 operation and corrupt the signature resistance. if unused, tie shdn to v portn . t2p (pin 2): type 2 pse indicator, open-drain. low imped - ance indicates the presence of a type 2 pse. r class (pin 3): class select input. connect a resistor between r class and v portn to set the classifcation load current (see table 2). nc (pins 4, 7, 8, 25, 28, 31): no connect. v portn (pins 5, 6): input voltage, negative rail. pin 5 and pin 6 must be electrically tied together at the package. sg (pin 9): synchronous gate drive output. this pin provides an output signal for a secondary-side synchro - nous rectifer. large dynamic currents may fow during voltage transitions. see the applications information section for details. v cc (pin 10): supply voltage pin. bypass this pin to gnd with a low esr ceramic capacitor. see the applica - tions information section for details. t on (pin 11): pin for external programming resistor to set the minimum time that the primary switch is on for each cycle. minimum turn-on facilitates the isolated feed - back method. see the applications information section for details. endly (pin 12): pin for external programming resistor to set enable delay time. the enable delay time disables the feedback amplifer for a fxed time after the turn-off of the primary-side mosfet. this allows the leakage inductance voltage spike to be ignored for fyback voltage sensing. see the applications information section for details. sync (pin 13): external sync input. this pin is used to synchronize the internal oscillator with an external clock. the positive edge of the clock causes the oscillator to dis - charge causing pg to go low (off) and sg high (on). the sync threshold is typically 1.5v. tie to ground if unused. see the applications information section for details. sfst (pin 14): soft-start. this pin, in conjunction with a capacitor (c sfst ) to gnd, controls the ramp-up of peak primary current through the sense resistor. it is also used to control converter inrush at start-up. the sfst clamps the v cmp voltage and thus limits peak current until soft- start is complete. the ramp time is approximately 70ms per f of capacitance. leave sfst open if not using the soft-start function. osc (pin 15): oscillator. this pin, in conjunction with an external capacitor (c osc ) to gnd, defnes the controller oscillator frequency. the frequency is approximately 100khz ? 100/c osc (pf). fb (pin 16): feedback amplifer input. feedback is usually sensed via a third winding and enabled during the fyback period. this pin also sinks additional current to compensate for load current variation as set by the r cmp pin. keep the thevenin equivalent resistance of the feedback divider at roughly 3k. v cmp (pin 17): frequency compensation control. v cmp is used for frequency compensation of the switcher con - trol loop. it is the output of the feedback amplifer and the input to the current comparator. switcher frequency compensation components are placed on this pin to gnd. the voltage on this pin is proportional to the peak primary switch current. the feedback amplifer output is enabled during the synchronous switch on time. uvlo (pin 18): undervoltage lockout. a resistive divider from v portp to this pin sets an undervoltage lockout based upon v portp level (not v cc ). when the uvlo pin is below its threshold, the gate drives are disabled, but the part draws its normal quiescent current from v cc . the bias current on this pin has hysteresis such that the bias current is sourced when uvlo threshold is exceeded. this introduces a hysteresis at the pin equivalent to the bias current change times the impedance of the upper divider resistor. the user can control the amount of hysteresis by adjusting the impedance of the divider. tie the uvlo pin to v cc if not using this function. see the applications ltc4278 11 4278fc information section for details. this pin is used for the uvlo function of the switching regulator. the pd interface section has an internal uvlo. sense C , sense + (pins 19, 20): current sense inputs. these pins are used to measure primary-side switch cur - rent through an external sense resistor. peak primary-side current is used in the converter control loop. make kelvin connections to the sense resistor r sense to reduce noise problems. sense C connects to the gnd side. at maximum current (v cmp at its maximum voltage) sense pins have 100mv threshold. the signal is blanked (ignored) during the minimum turn-on time. c cmp (pin 21): load compensation capacitive control. connect a capacitor from c cmp to gnd in order to reduce the effects of parasitic resistances in the feedback sensing path. a 0.1f ceramic capacitor suffces for most applica - tions. short this pin to gnd when load compensation is not needed. r cmp (pin 22): load compensation resistive control. connect a resistor from r cmp to gnd in order to com - pensate for parasitic resistances in the feedback sensing path. in less demanding applications, this resistor is not needed and this pin can be left open. see the applications information section for details. pin functions pgdly (pin 23): primary gate delay control. connect an external programming resistor (r pgdly ) to set delay from synchronous gate turn-off to primary gate turn-on. see the applications information section for details. pg (pin 24): primary gate drive. pg is the gate drive pin for the primary-side mosfet switch. large dynamic cur - rents fow during voltage transitions. see the applications information section for details. v neg (pins 26, 27): system negative rail. connects v neg to v portn through an internal power mosfet. pin 26 and pin 27 must be electrically tied together at the package. pwrgd (pin 29): power good output, open-collector. high impedance signals power-up completion. pwrgd is referenced to v neg and features a 14v clamp. pwrgd (pin 30): complementary power good output, open-drain. low impedance signals power-up completion. pwrgd is referenced to v portn . v portp (pin 32): positive power input. tie to the input port power through the input diode bridge. exposed pad (pin 33): ground. this is the negative rail connection for both signal ground and gate driver grounds of the fyback controller. this pin should be connected to v neg . ltc4278 12 4278fc block diagram 19 sense ? 20 sense + c cmp 3v to fb pgate sgate current sense amp r cmpf 50k load compensation ? + ? + ? + ? + ? + ? + ? + uvlo 0.8v disable i uvlo 18 osc 15 t on 11 pgdly 23 endly nc 12 sync 13 1.237v reference (v fb ) internal regulator uvlo 3v collapse detect error amp clamps 0.7 1.3 + ? s r q q 1v 16 fb 17 v cmp 14 sfst tsd current trip slope compensation current comparator overcurrent fault logic block ? + ? + 21 r cmp gate drive 22 pg 24 sg 9 gnd (exposed pad) 33 oscillator set enable gate drive bold line indicates high current path 14v 32 t2p 2 r class 3 nc 4 shdn pwrgd v portp 31 nc 1 30 pwrgd 29 25 nc 28 v neg v neg 26 control circuits classification current load 1.237v ? + 16k 25k 7 v portn nc 8 nc 10 v cc 6 27 4278 bd v portn 5 ltc4278 13 4278fc applications information overview power over ethernet (poe) continues to gain popularity as more products are taking advantage of having dc power and high speed data available from a single rj45 connector. as poe continues to grow in the marketplace, powered device (pd) equipment vendors are running into the 12.95w power limit established by the ieee 802.3af standard. the iee802.3at standard establishes a higher power alloca - tion for power over ethernet while maintaining backwards compatibility with the existing ieee 802.3af systems. power sourcing equipment (pse) and powered devices are distinguished as type 1 complying with the ieee 802.3af/ ieee 802.3at power levels, or type 2 complying with the ieee 802.3at power levels. the maximum available power of a type 2 pd is 25.5w. the ieee 802.3at standard also establishes a new method of acquiring power classifcation from a pd and communi - cating the presence of a type 2 pse. a type 2 pse has the option of acquiring pd power classifcation by performing 2-event classifcation (layer 1) or by communicating with the pd over the data line (layer 2). in turn, a type 2 pd must be able to recognize both layers of communications and identify a type 2 pse. the ltc4278 is specifcally designed to support the front end of a pd that must operate under the ieee 802.3at standard. in particular, the ltc4278 provides the t2p indicator bit which recognizes 2-event classifcation. this indicator bit may be used to alert the ltc4278 output load that a type 2 pse is present. with an internal signature resistor, classifcation circuitry, inrush control, and ther - mal shutdown, the ltc4278 is a complete pd interface solution capable of supporting in the next generation pd applications. modes of operation the ltc4278 has several modes of operation depending on the input voltage applied between the v portp and v portn pins. figure 1 presents an illustration of voltage and current waveforms the ltc4278 may encounter with the various modes of operation summarized in table 1. detection v1 classification on off off power bad off on = r load c1 pwrgd tracks v portn detection v2 50 time 40 30 v portp (v) 20 10 50 40 30 20 10 time v portp ? v neg (v) ?10 time ?20 ?30 v portp ? pwrgd (v) pwrgd ? v neg (v) ?40 ?50 20 10 pd current inrush dv dt inrush c1 = power bad pwrgd tracks v portp pwrgd tracks v portp power bad power bad time time power good power good detection i 1 classification detection i 2 load, i load 4278 f01 i class dependent on r class selection inrush = 100ma i 1 = v1 ? 2 diode drops 25k i load = v portp r load i 2 = v2 ? 2 diode drops 25k v portp pse i in r load r class c1 r class pwrgd pwrgd ltc4278 v neg v portn in detection range figure 1. v neg , pwrgd , pwrgd and pd current as a function of input voltage ltc4278 14 4278fc applications information table 1. ltc4278 modes of operation as a function of input voltage v portp Cv portn (v) ltc4278 modes of operation 0v to 1.4v inactive (reset after 1st classifcation event) 1.5v to 9.8v (5.4v to 9.8v) 25k signature resistor detection before 1st classifcation event (mark, 11k signature corrupt after 1st classifcation event) 12.5v to on/off* classifcation load current active on/off* to 60v inrush and power applied to pd load >71v overvoltage lockout, classifcation and hot swap are disabled *on/off includes hysteresis. rising input threshold, 37.2v max. falling input threshold, 30v min. these modes satisfy the requirements defned in the ieee 802.3af/ieee 802.3at specifcation. input diode bridge in the ieee 802.3af/ieee 802.3at standard, the modes of operation reference the input voltage at the pds rj45 connector. since the pd must handle power received in either polarity from either the data or the spare pair, input diode bridges br1 and br2 are connected between the rj45 connector and the ltc4278 (figure 2). the input diode bridge introduces a voltage drop that affects the range for each mode of operation. the ltc4278 compensates for these voltage drops so that a pd built with the ltc4278 meets the ieee 802.3af/ieee 802.3at-established voltage ranges. note the electrical characteristics are referenced with respect to the ltc4278 package pins. detection during detection, the pse looks for a 25k signature resis - tor which identifes the device as a pd. the pse will apply two voltages in the range of 2.8v to 10v and measures the corresponding currents. figure 1 shows the detection voltages v1 and v2 and the corresponding pd current. the pse calculates the signature resistance using the v/ i measurement technique. the ltc4278 presents its precision, temperature-compen - sated 25k resistor between the v portp and v portn pins, alerting the pse that a pd is present and requests power to be applied. the ltc4278 signature resistor also com - pensates for the additional series resistance introduced by the input diode bridge. thus a pd built with the ltc4278 conforms to the ieee 802.3af/ieee 802.3at specifcations. rx ? 6 rx + 3 tx ? 2 tx + rj45 t1 powered device (pd) input 4278 f02 1 7 8 5 4 spare ? spare + to phy br2 0.1f 100v br1 d3 ltc4278 v portn v portp figure 2. pd front end using diode bridges on main and spare inputs ltc4278 15 4278fc applications information signature corrupt option in some designs that include an auxiliary power option, it is necessary to prevent a pd from being detected by a pse. the ltc4278 signature resistance can be corrupted with the shdn pin (figure 3). taking the shdn pin high will reduce the signature resistor below 11k which is an invalid signature per the ieee 802.3af/ieee 802.3at speci - fcation, and alerts the pse not to apply power. invoking the shdn pin also ceases operation for classifcation and disconnects the ltc4278 load from the pd input. if this feature is not used, connect shdn to v portn . table 2. summary of power classifcations and ltc4278 r class resistor selection class usage maximum power levels at input of pd (w) nominal classification load current (ma) ltc4278 r class resistor (, 1%) 0 type 1 0.44 to 12.95 < 0.4 open 1 type 1 0.44 to 3.84 10.5 124 2 type 1 3.84 to 6.49 18.5 69.8 3 type 1 6.49 to 12.95 28 45.3 4 type 2 12.95 to 25.5 40 30.9 2-event classification and the t2p pin a type 2 pse may declare the availability of high power by performing a 2-event classifcation (layer 1) or by com - municating over the high speed data line (layer 2). a type 2 pd must recognize both layers of communication. since layer 2 communication takes place directly between the pse and the ltc4278 load, the ltc4278 concerns itself only with recognizing 2-event classifcation. in 2-event classifcation, a type 2 pse probes for power classifcation twice. figure 4 presents an example of a 2-event classifcation. the 1st classifcation event occurs when the pse presents an input voltage between 15.5v to 20.5v and the ltc4278 presents a class 4 load cur - rent. the pse then drops the input voltage into the mark voltage range of 7v to 10v, signaling the 1st mark event. the pd in the mark voltage range presents a load current between 0.25ma to 4ma. the pse repeats this sequence, signaling the 2nd clas - sifcation and 2nd mark event occurrence. this alerts the ltc4278 that a type 2 pse is present. the type 2 pse then applies power to the pd and the ltc4278 charges up the reservoir capacitor c1 with a controlled inrush cur - rent. when c1 is fully charged, and the ltc4278 declares power good, the t2p pin presents an active low signal, or low impedance output with respect to v portn . the t2p output becomes inactive when the ltc4278 input voltage falls below undervoltage lockout threshold. figure 3. 25k signature resistor with disable v portp v portn shdn ltc4278 signature disable 4278 f03 25k signature resistor 16k to pse classification classifcation provides a method for more effcient power allocation by allowing the pse to identify a pd power clas - sifcation. class 0 is included in the ieee specifcation for pds that do not support classifcation. class 1-3 partitions pds into three distinct power ranges. class 4 includes the new power range under ieee802.3at (see table 2). during classifcation probing, the pse presents a fxed voltage between 15.5v and 20.5v to the pd (figure 1). the ltc4278 asserts a load current representing the pd power classifcation. the classifcation load current is programmed with a resistor r class that is chosen from table 2. ltc4278 16 4278fc applications information detection v1 on off off off on = r load c1 tracks v portn detection v2 time pd current 50 40 30 v portp (v) 20 10 40ma 50 40 30 20 10 time v portp ? v neg (v) ?10 time ?20 ?30 v portp ? t2p (v) ?40 ?50 dv dt inrush c1 = 4278 f04 inrush = 100ma r class = 30.9 i load = v portn r load v portp pse i in r load r class c1 r class t2p ltc4278 v neg v portn 1st class 1st mark 2nd mark detection v1 detection v2 1st mark 2nd mark 2nd class 1st class 2nd class load, i load inrush figure 4. v neg , t2p and pd current as a result of 2-event classifcation signature corrupt during mark as a member of the ieee 802.3at working group, linear technology noted that it is possible for a type 2 pd to receive a false indication of a 2-event classifcation if a pse port is pre-charged to a voltage above the detection voltage range before the frst detection cycle. the ieee working group modifed the standard to prevent this pos - sibility by requiring a type 2 pd to corrupt the signature resistance during the mark event, alerting the pse not to apply power. the ltc4278 conforms to this standard by corrupting the signature resistance. this also discharges the port before the pse begins the next detection cycle. pd stability during classification classifcation presents a challenging stability problem due to the wide range of possible classifcation load current. the onset of the classifcation load current introduces a voltage drop across the cable and increases the forward voltage of the input diode bridge. this may cause the pd to oscillate between detection and classifcation with the onset and removal of the classifcation load current. the ltc4278 prevents this oscillation by introducing a voltage hysteresis window between the detection and clas - sifcation ranges. the hysteresis window accommodates the voltage changes a pd encounters at the onset of the classifcation load current, thus providing a trouble-free transition between detection and classifcation modes. the ltc4278 also maintains a positive i-v slope throughout the classifcation range up to the on-voltage. in the event a pse overshoots beyond the classifcation voltage range, the available load current aids in returning the pd back into the classifcation voltage range. (the pd input may otherwise be trapped by a reverse-biased diode bridge and the voltage held by the 0.1f capacitor). inrush current once the pse detects and optionally classifes the pd, the pse then applies powers on the pd. when the ltc4278 input voltage rises above the on-voltage threshold, ltc4278 connects v neg to v portn through the internal power mosfet. ltc4278 17 4278fc applications information to control the power-on surge currents in the system, the ltc4278 provides a fxed inrush current, allowing c1 to ramp up to the line voltage in a controlled manner. the ltc4278 keeps the pd inrush current below the pse current limit to provide a well controlled power-up charac - teristic that is independent of the pse behavior. this ensures a pd using the ltc4278 interoperability with any pse. turn-on/ turn-off threshold the ieee 802.3af/at specifcation for the pd dictates a maximum turn-on voltage of 42v and a minimum turn-off voltage of 30v. this specifcation provides an adequate voltage to begin pd operation, and to discontinue pd operation when the input voltage is too low. in addition, this specifcation allows pd designs to incorporate an on/ off hysteresis window to prevent start-up oscillations. the ltc4278 features an on/off hysteresis window (see figure 5) that conforms with the ieee 802.3af/at specif - cation and accommodates the voltage drop in the cable and input diode bridge at the onset of the inrush current. once c1 is fully charged, the ltc4278 turns on is internal mosfet and passes power to the pd load. the ltc4278 continues to power the pd load as long as the input voltage does not fall below the off threshold. when the ltc4278 input voltage falls below the off threshold, the pd load figure 5. ltc4278 on/off and overvoltage lockout v portp c1 5f min v portn v neg ltc4278 4278 f05 to pse on/off and overvoltage lockout circuit pd load current-limited turn on + v portp ? v portn ltc4278 voltage power mosfet 0v to on* off >on* on ltc4278 18 4278fc pwrgd pin when shdn is invoked in pd applications where an auxiliary power supply invokes the shdn feature, the pwrgd pin becomes high imped - ance. this prevents the pwrgd pin that is connected to the uvlo pin from interfering with the dc/dc converter operations when powered by an auxiliary power supply. overvoltage lockout the ltc4278 includes an overvoltage lockout (ovlo) feature (figure 6) which protects the ltc4278 and its load from an overvoltage event. if the input voltage exceeds the ovlo threshold, the ltc4278 discontinues pd operation. normal operations resume when the input voltage falls below the ovlo threshold and when c1 is charged up. thermal protection the ieee 802.3af/at specifcation requires a pd to withstand any applied voltage from 0v to 57v indefnitely. however, there are several possible scenarios where a pd may encounter excessive heating. during classifcation, excessive heating may occur if the pse exceeds the 75ms probing time limit. at turn-on, when the load capacitor begins to charge, the instantaneous power dissipated by the pd interface can be large before it reaches the line voltage. and if the pd experiences a fast input positive voltage step in its operational mode (for example, from 37v to 57v), the instantaneous power dissipated by the pd interface can be large. the ltc4278 includes a thermal protection feature which protects the ltc4278 from excessive heating. if the ltc4278 junction temperature exceeds the over-temper - ature threshold, the ltc4278 discontinues pd operations and power good becomes inactive. normal operation resumes when the junction temperature falls below the overtemperature threshold and when c1 is charged up. external interface and component selection transformer nodes on an ethernet network commonly interface to the outside world via an isolation transformer. for pds, the isolation transformer must also include a center tap on the rj45 connector side (see figure 7). the increased current levels in a type 2 pd over a type 1 increase the current imbalance in the magnetics which can interfere with data transmission. in addition, proper termination is also required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. transformer vendors such as bel fuse, coilcraft, halo, pulse, and tyco (table 4) can assist in selecting an appropriate isolation transformer and proper termination methods. table 4. power over ethernet transformer vendors vendor contact information bel fuse inc. 206 van vorst street jersey city, nj 07302 tel: 201-432-0463 www.belfuse.com coilcraft inc. 1102 silver lake road gary, il 60013 tel: 847-639-6400 www.coilcraft.com halo electronics 1861 landings drive mountain view, ca 94043 tel: 650-903-3800 www.haloelectronics.com pca electronics 16799 schoenborn street north hills, ca 91343 tel: 818-892-0761 www.pca.com pulse engineering 12220 world trade drive san diego, ca 92128 tel: 858-674-8100 www.pulseeng.com tyco electronics 308 constitution drive menlo park, ca 94025-1164 tel: 800-227-7040 www.circuitprotection.com input diode bridge figure 2 shows how two diode bridges are typically con - nected in a pd application. one bridge is dedicated to the data pair while the other bridge is dedicated to the spare pair. the ltc4278 supports the use of either silicon or schottky input diode bridges. however, there are tradeoffs in the choice of diode bridges. applications information ltc4278 19 4278fc an input diode bridge must be rated above the maximum current the pd application will encounter at the tempera - ture the pd will operate. diode bridge vendors typically call out the operating current at room temperature, but derate the maximum current with increasing temperature. consult the diode bridge vendors for the operating current derating curve. a silicon diode bridge can consume over 4% of the available power in some pd applications. using schottky diodes can help reduce the power loss with a lower forward voltage. a schottky bridge may not be suitable for some high temperature pd application. the leakage current has a voltage dependency that can reduce the perceived signature resistance. in addition, the ieee 802.3af/at specifcation mandates the leakage back-feeding through the unused bridge cannot generate more than 2.8v across a 100k resistor when a pd is powered with 57v. sharing input diode bridges at higher temperatures, a pd design may be forced to consider larger bridges in a bigger package because the maximum operating current for the input diode bridge is drastically derated. the larger package may not be accept- able in some space-limited environments. one solution to consider is to reconnect the diode bridges so that only one of the four diodes conducts current in each package. this confguration extends the maximum operating current while maintaining a smaller package profle. figure 7 shows how to reconnect the two diode bridges. consult the diode bridge vendors for the derating curve when only one of four diodes is in operation. input capacitor the ieee 802.3af/at standard includes an impedance requirement in order to implement the ac disconnect function. a 0.1f capacitor (c14 in figure 7) is used to meet this ac impedance requirement. transient voltage suppressor the ltc4278 specifes an absolute maximum voltage of 100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world can routinely see excessive peak voltages. to protect the ltc4278, install a transient voltage suppressor (d3) be - tween the input diode bridge and the ltc4278 as shown in figure 7. applications information figure 7. pd front-end with isolation transformer, diode bridges, capacitors, and a transient voltage suppressor (tvs) 14 13 12 1 2 3 rx ? 6 rx + 3 tx ? 2 tx + rj45 t1 coilcraft ethi - 230ld 4278 f07 1 7 8 5 4 10 9 11 5 6 4 d3 smaj58a tvs b1100 br1 hd01 br2 hd01 to phy v portp ltc4278 c1 v portn v neg spare ? spare + c14 0.1f 100v ltc4278 20 4278fc classifcation resistor (r class ) the r class resistor sets the classifcation load current, corresponding to the pd power classifcation. select the value of r class from table 2 and connect the resistor between the r class and v portn pins as shown in figure 4, or foat the r class pin if the classifcation load cur - rent is not required. the resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classifcation circuit. load capacitor the ieee 802.3af/at specifcation requires that the pd maintains a minimum load capacitance of 5f and does not specify a maximum load capacitor. however, if the load capacitor is too large, there may be a problem with inadvertent power shutdown by the pse. this occurs when the pse voltage drops quickly. the input diode bridge reverses bias, and the pd load momentarily powers off the load capacitor. if the pd does not draw power within the pses 300ms disconnection delay, the pse may remove power from the pd. thus, it is necessary to evaluate the load current and capacitance to ensure that an inadvertent shutdown cannot occur. the load capacitor can store signifcant energy when fully charged. the pd design must ensure that this energy is not inadvertently dissipated in the ltc4278. for example, if the v portp pin shorts to v portn while the capacitor is charged, current will fow through the parasitic body diode of the internal mosfet and may cause permanent damage to the ltc4278. t2p interface when a 2-event classifcation sequence successfully completes, the ltc4278 recognizes this sequence, and provides an indicator bit, declaring the presence of a type 2 pse. the open-drain output provides the option to use this signal to communicate to the ltc4278 load, or to leave the pin unconnected. figure 8 shows two interface options using the t2p pin and the opto-isolator. the t2p pin is active low and con - nects to an opto-isolator to communicate across the dc/ dc converter isolation barrier. the pull-up resistor r p is sized according to the requirements of the opto-isolator operating current, the pull-down capability of the t2p pin, and the choice of v + . v + for example can come from the poe supply rail (which the ltc4278 v portp is tied to), or from the voltage source that supplies power to the dc/ dc converter. option 1 has the advantage of not drawing power unless t2p is declared active. shutdown interface to corrupt the signature resistance, the shdn pin can be driven high with respect to v portn . if unused, connect shdn directly to v portn . auxiliary power source in some applications, it is desirable to power the pd from an auxiliary power source such as a wall adapter. auxiliary power can be injected into an ltc4278-based pd at the input of the ltc4278 v portn , at v neg , or even the power supply output. in addition, some pd applications may desire auxiliary supply dominance or may be confgured applications information 4278 f08 option 1: series configuration for active low/low impedance output ?54v to pse r p to pd load v portp ltc4278 v portn t2p v + option 2: shunt configuration for active high/open collector output ?54v to pse r p to pd load v portp ltc4278 v portn v neg t2p v + figure 8. t2p interface examples ltc4278 21 4278fc for poe dominance. furthermore, pd applications may also opt for a seamless transition that is, without power disruption between poe and auxiliary power. the most common auxiliary power option injects power at v neg . figure 9 presents an example of this application. in this example, the auxiliary port injects 48v onto the line via diode d1. the components surrounding the shdn pin are selected so that the ltc4278 does not disconnect power to the output until the auxiliary supply exceeds 36v. this confguration is an auxiliary-dominant confguration. that is, the auxiliary power source supplies the power even if poe power is already present. this confguration also provides a seamless transition from poe to auxiliary power when auxiliary power is applied, however, the removal of auxiliary power to poe power is not seamless. contact linear technology applications support for detail information on implementing a custom auxiliary power supply. ieee 802.3at system power-up requirement under the ieee 802.3at standard, a pd must operate under 1 2.95w in accordance with ieee 802.3at standard until it recognizes a type 2 pse. initializing pd operation in 12.95w mode eliminates interoperability issue in case a type 2 pd connects to a type 1 pse. once the pd recognizes a type 2 pse, the ieee 802.3at standard requires the pd to wait 80ms in 12.95w operation before 25.5w operation can commence. maintain power signature in an ieee 802.3af/at system, the pse uses the maintain power signature (mps) to determine if a pd continues to require power. the mps requires the pd to periodically draw at least 10ma and also have an ac impedance less than 26.25k in parallel with 0.05f. if one of these condi - tions is not met, the pse may disconnect power to the pd. switching regulator overview the ltc4278 includes a current mode converter designed specifcally for use in an isolated fyback topology employing synchronous rectifcation. the ltc4278 operation is similar to traditional current mode switchers. the major difference is that output voltage feedback is derived via sensing the output voltage through the transformer. this precludes the need of an opto-isolator in isolated designs, thus greatly improving dynamic response and reliability. the ltc4278 has a unique feedback amplifer that samples a transformer winding voltage during the fyback period and uses that voltage to control output voltage. the internal blocks are similar to many current mode controllers. the differences lie in the feedback amplifer and load applications information figure 9. auxiliary power dominant pd interface example t1 4278 f09 tvs to phy 36v 100k 10k 10k d1 br1 + ? br2 + ? 0.1f 100v c1 v portp ltc4278 v portn shdn v neg gnd + ? isolated wall transformer rx ? 6 rx + 3 tx ? 2 tx + rj45 1 7 8 5 4 spare ? spare + ltc4278 22 4278fc compensation circuitry. the logic block also contains circuitry to control the special dynamic requirements of fyback control. for more information on the basics of current mode switcher/controllers and isolated fyback converters see application note 19. feedback ampliferpseudo dc theory for the following discussion, refer to the simplifed switching regulator feedback amplifer diagram (figure 10a). when the primary-side mosfet switch mp turns off, its drain voltage rises above the v portp rail. flyback occurs when the primary mosfet is off and the synchronous secondary mosfet is on. during fyback the voltage on nondriven transformer pins is determined by the secondary voltage. the amplitude of this fyback pulse, as seen on the third winding, is given as: v flbk = v out + i sec ? esr + r ds(on) ( ) n sf r ds(on) = on-resistance of the synchronous mosfet ms i sec = transformer secondary current esr = impedance of secondary circuit capacitor, winding and traces n sf = transformer effective secondary-to-fyback winding turns ratio (i.e., n s /n flbk ) the fyback voltage is scaled by an external resistive divider r1/r2 and presented at the fb pin. the feedback amplifer compares the voltage to the internal bandgap reference. the feedback amp is actually a transconductance amplifer whose output is connected to v cmp only during a period in the fyback time. an external capacitor on the v cmp pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point. the regulation voltage at the fb pin is nearly equal to the bandgap reference v fb because of the high gain in the overall loop. the relationship between v flbk and v fb is expressed as: v flbk = r1 + r2 r2 ? v fb applications information combining this with the previous v flbk expression yields an expression for v out in terms of the internal reference, programming resistors and secondary resistances: v out = r1 + r2 r2 ? v fb ? n sf ? ? ? ? ? ? ? i sec ? esr + r ds(on) ( ) the effect of nonzero secondary output impedance is discussed in further detail (see load compensation theory). the practical aspects of applying this equation for v out are found in subsequent sections of the applications information. feedback amplifer dynamic theory so far, this has been a pseudo-dc treatment of fyback feedback amplifer operation. but the fyback signal is a pulse, not a dc level. provision is made to turn on the fyback amplifer only when the fyback pulse is present, using the enable signal as shown in the timing diagram (figure 10b). minimum output switch on time (t on(min) ) the ltc4278 affects output voltage regulation via fyback pulse action. if the output switch is not turned on, there is no fyback pulse and output voltage information is not available. this causes irregular loop response and start-up/latchup problems. the solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. to accomplish this the current limit feedback is blanked each cycle for t on(min) . if the output load is less than that developed under these conditions, forced continuous operation normally occurs. see subsequent discussions in the applications information section for further details. enable delay time (endly) th e fyback pulse appears when the primary-side switch shuts off. however, it takes a fnite time until the transformer primary-side voltage waveform represents the output voltage. this is partly due to rise time on the primary- side mosfet drain node, but, more importantly, is due ltc4278 23 4278fc applications information + ? v fb 1.237v enable collapse detect 1v ltc4278 feedback amp fb r1 r2 16 17 v cmp v in primary flyback secondary ? ? ? mp t1 v flbk ms c vcmp 4278 f10a c out isolated output + s r q ? + primary-side mosfet drain voltage pg voltage sg voltage v in t on(min) enable delay min enable feedback amplifier enabled pg delay 4278 f10b v flbk 0.8 ? v flbk figure 10a. ltc4278 switching regulator feedback amplifer figure 10b. ltc4278 switching regulator timing diagram ltc4278 24 4278fc to transformer leakage inductance. the latter causes a voltage spike on the primary side, not directly related to output voltage. some time is also required for internal settling of the feedback amplifer circuitry. in order to maintain immunity to these phenomena, a fxed delay is introduced between the switch turn-off command and the enabling of the feedback amplifer. this is termed enable delay. in certain cases where the leakage spike is not suffciently settled by the end of the enable delay period, regulation error may result. see the subsequent sections for further details. collapse detect once the feedback amplifer is enabled, some mechanism is then required to disable it. this is accomplished by a collapse detect comparator, which compares the fyback voltage (fb) to a fxed reference, nominally 80% of v fb . when the fyback waveform drops below this level, the feedback amplifer is disabled. minimum enable time the feedback amplifer, once enabled, stays on for a fxed minimum time period, termed minimum enable time. this prevents lockup, especially when the output voltage is abnormally low, e.g., during start-up. the minimum enable time period ensures that the v cmp node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. this time is set internally. effects of variable enable period the feedback amplifer is enabled during only a portion of the cycle time. this can vary from the fxed minimum enable time described to a maximum of roughly the off switch time minus the enable delay time. certain parameters of feedback amp behavior are directly affected by the variable enable period. these include effective transconductance and v cmp node slew rate. load compensation theory the ltc4278 uses the fyback pulse to obtain information about the isolated output voltage. an error source is caused by transformer secondary current fow through the synchronous mosfet r ds(on) and real life nonzero impedances of the transformer secondary and output capacitor. this was represented previously by the expression, i sec ? (esr + r ds(on) ). however, it is generally more useful to convert this expression to effective output impedance. because the secondary current only fows during the off portion of the duty cycle (dc), the effective output impedance equals the lumped secondary impedance divided by off time dc. since the off-time duty cycle is equal to 1 C dc, then: r s(out) = esr + r ds(on) 1 C dc where: r s(out) = effective supply output impedance dc = duty cycle r ds(on) and esr are as defned previously this impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. in these cases, the external fb resistive divider is adjusted to compensate for nominal expected error. in more demanding applications, output impedance error is minimized by the use of the load compensation function. figure 11 shows the block diagram of the load compensation function. switch current is converted to a voltage by the external sense resistor, averaged and lowpass fltered by the internal 50k resistor r cmpf and the external capacitor on c cmp . this voltage is impressed across the external r cmp resistor by op amp a1 and transistor q3 producing a current at the collector of q3 that is subtracted from the fb node. this effectively increases the voltage required at the top of the r1/r2 feedback divider to achieve equilibrium. the average primary-side switch current increases to maintain output voltage regulation as output loading increases. the increase in average current increases r cmp resistor current which affects a corresponding increase in sensed output voltage, compensating for the ir drops. applications information ltc4278 25 4278fc assuming relatively fxed power supply effciency, eff, power balance gives: p out = eff ? p in v out ? i out = eff ? v in ? i in average primary-side current is expressed in terms of output current as follows: i in = k1 ? i out where: k1= v out v in ? eff so, the effective change in v out target is: v out = k1 ? r sense r cmp ? r1 ? n sf ? i out thus: v out i out = k1 ? r sense r cmp ? r1 ? n sf where: k1 = dimensionless variable related to v in , v out and effciency , as previously explained r sense = external sense resistor nominal output impedance cancellation is obtained by equating this expression with r s(out) : k1 ? r sense r cmp ? r1 ? n sf = esr + r ds(on) 1 C dc solving for r cmp gives: r cmp = k1 ? r sense ? 1 C dc ( ) esr + r ds(on) ? r1 ? n sf the practical aspects of applying this equation to determine an appropriate value for the r cmp resistor are discussed subsequently in the applications information section. transformer design transformer design/specifcation is the most critical part of a successful application of the ltc4278. the following sections provide basic information about designing the transformer and potential tradeoffs. if you need help, the ltc applications group is available to assist in the choice and/or design of the transformer. turns ratios the design of the transformer starts with determining duty cycle (dc). dc impacts the current and voltage stress on the power switches, input and output capacitor rms currents and transformer utilization (size vs power). the ideal turns ratio is: n iideal = v out v in ? 1 C dc dc avoid extreme duty cycles , as they generally increase cur - rent stresses. a reasonable target for duty cycle is 50% at nominal input voltage. for instance, if we wanted a 48v to 5v converter at 50% dc then: n iideal = 5 48 ? 1? 0.5 0.5 = 1 9.6 in general, better performance is obtained with a lower turns ratio. a dc of 45.5% yields a 1:8 ratio. applications information ? ? ? mp r cmpf 50k v in v flbk r2 load comp i r1 fb v fb q1 q2 r cmp c cmp r sense sense + 4278 f11 q3 ? + a1 16 22 21 20 figure 11. load compensation diagram ltc4278 26 4278fc note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance. when building a supply with multiple outputs derived through a multiple winding transformer, lower duty cycle can improve cross regulation by keeping the synchronous rectifer on longer, and thus, keep secondary windings coupled longer. for a multiple output transformer, the turns ratio between output windings is critical and affects the accuracy of the voltages. the ratio between two output voltages is set with the formula v out2 = v out1 ? n21 where n21 is the turns ratio between the two windings. also keep the secondary mosfet r ds(on) small to improve cross regulation. the feedback winding usually provides both the feedback voltage and power for the ltc4278. set the turns ratio between the output and feedback winding to provide a rectifed voltage that under worst-case conditions is greater than the the preregulator maximum supply voltage. for example if the preregulator maximum output were 7v: n sf > v out 7 + v f where: v f = diode forward voltage for our example: n sf > 5 7 + 0.7 = 1 1.56 we will choose 1 3 leakage inductance transformer leakage inductance (on either the primary or secondary) causes a spike after the primary-side switch turn-off. this is increasingly prominent at higher load currents, where more stored energy is dissipated. higher fyback voltage may break down the mosfet switch if it has too low a bv dss rating. one solution to reducing this spike is to use a clamp circuit to suppress the voltage excursion. however, suppressing the voltage extends the fyback pulse width. if the fyback pulse extends beyond the enable delay time, output voltage regulation is affected. the feedback system has a deliberately limited input range, roughly 50mv referred to the fb node. this rejects higher voltage leakage spikes because once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. therefore, it is advisable to arrange the clamp circuit to clamp at as high a voltage as possible, observing mosfet breakdown, such that leakage spike duration is as short as possible. application note 19 provides a good reference on clamp design. as a rough guide, leakage inductance of several percent (of mutual inductance) or less may require a clamp, but exhibit little to no regulation error due to leakage spike behavior. inductances from several percent up to, perhaps, ten percent, cause increasing regulation error. avoid double digit percentage leakage inductances. there is a potential for abrupt loss of control at high load cur - rent. this curious condition potentially occurs when the leakage spike becomes such a large portion of the fyback waveform that the processing circuitry is fooled into think - ing that the leakage spike itself is the real fyback signal! it then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. this typically reduces the output voltage abruptly to a fraction, roughly one-third to two-thirds of its correct value. once load current is reduced suffciently, the system snaps back to normal operation. when using transformers with considerable leakage inductance, exercise this worst-case check for potential bistability: 1. operate the prototype supply at maximum expected load current. 2. temporarily short-circuit the output. 3. observe that normal operation is restored. if the output voltage is found to hang up at an abnormally l ow value, the system has a problem. this is usually evident by simultaneously viewing the primary-side mosfet drain voltage to observe frsthand the leakage spike behavior. applications information ltc4278 27 4278fc applications information a fnal notethe susceptibility of the system to bistable behavior is somewhat a function of the load current/ voltage characteristics. a load with resistivei.e., i = v/r behavioris the most apt to be bistable. capacitive loads that exhibit i = v 2 /r behavior are less susceptible. secondary leakage inductance leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the fyback pulse. this increases the output voltage target by a similar percentage. note that unlike leakage spike behavior, this phenomenon is independent of load. since the secondary leakage inductance is a constant percentage of mutual inductance (within manufacturing variations), the solution is to adjust the feedback resistive divider ratio to compensate. winding resistance effects primary or secondary winding resistance acts to reduce overall effciency (p out /p in ). secondary winding resistance increases effective output impedance, degrading load regulation. load compensation can mitigate this to some extent but a good design keeps parasitic resistances low. biflar winding a biflar, or similar winding, is a good way to minimize troublesome leakage inductances. biflar windings also improve coupling coeffcients, and thus improve cross regulation in multiple winding transformers. however, tight coupling usually increases primary-to-secondary capacitance and limits the primary-to-secondary breakdown voltage, so is not always practical. primary inductance the transformer primary inductance, l p , is selected based on the peak-to-peak ripple current ratio (x) in the transformer relative to its maximum value. as a general rule, keep x in the range of 20% to 40% (i.e., x = 0.2 to 0.4). higher values of ripple will increase conduction losses, while lower values will require larger cores. ripple current and percentage ripple is largest at minimum duty cycle; in other words, at the highest input voltage. l p is calculated from the following equation. l p = v in(max) ? dc min ( ) 2 f osc ? x max ? p in = v in(max) ? dc min ( ) 2 ? eff f osc ? x max ? p out where: f osc is the oscillator frequency dc min is the dc at maximum input voltage x max is ripple current ratio at maximum input voltage using common high power poe values, a 48v (41v < v in < 57v) to 5v/5.3a converter with 90% effciency, p out = 26.5w and p in = 29.5w. using x = 0.4 n = 1/8 and f osc = 200khz: dc min = 1 1 + n ? v in(max) v out = 1 1 + 1 8 ? 57 5 = 41.2% l p = 57v ? 0.412 ( ) 2 200khz ? 0.4 ? 26.5w = 260 h optimization might show that a more effcient solution is obtained at higher peak current but lower inductance and the associated winding series resistance. a simple spreadsheet program is useful for looking at tradeoffs. transformer core selection once l p is known, the type of transformer is selected. high effciency converters use ferrite cores to minimize core loss. actual core loss is independent of core size for a fxed inductance, but decreases as inductance increases. since increased inductance is accomplished through more turns of wire, copper losses increase. thus, transformer design balances core and copper losses. remember that increased winding resistance will degrade cross regulation and increase the amount of load compensation required. the main design goals for core selection are reducing copper losses and preventing saturation. ferrite core material saturates hard, rapidly reducing inductance ltc4278 28 4278fc applications information when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and, consequently, output voltage ripple. do not allow the core to saturate! the maximum peak primary current occurs at minimum v in : i pk = p in v in(min) ? dc max ? 1 + x min 2 ? ? ? ? ? ? now : dc max = 1 1 + n ? v in min ( ) v out = 1 1 + 1 8 ? 41 5 = 49.4% x min = v in(min) ? dc max ( ) 2 f osc ? l p ? p in = 41 ? 49.4% ( ) 2 200khz ? 260 h ? 29.5w = 0.267 using the example numbers leads to: i pk = 29.5w 41 ? 0.494 ? 1 + 0.267 2 ? ? ? ? ? ? = 1.65a multiple outputs one advantage that the fyback topology offers is that additional output voltages can be obtained simply by adding windings. designing a transformer for such a situation is beyond the scope of this document. for multiple windings, realize that the fyback winding signal is a combination of activity on all the secondary windings. thus load regulation is affected by each windings load. take care to minimize cross regulation effects. setting feedback resistive divider the expression for v out developed in the operation section is rearranged to yield the following expression for the feedback resistors: r1 = r2 v out + i sec ? esr + r ds(on) ( ) ? ? ? ? v fb ? n sf ? 1 ? ? ? ? ? ? ? ? continuing the example, if esr + r ds(on) = 8m<, r2 = 3.32k, then: r1 = 3.32k 5 + 5.3 ? 0.008 1.237 ? 1/ 3 ? 1 ? ? ? ? ? ? = 37.28k choose 37.4k. it is recommended that the thevenin impedance of the resistive divider (r1||r2) is roughly 3k for bias current cancellation and other reasons. current sense resistor considerations the external current sense resistor is used to control peak primary switch current, which controls a number of key converter characteristics including maximum power and external component ratings. use a noninductive current sense resistor (no wire-wound resistors). mounting the resistor directly above an unbroken ground plane connected with wide and short traces keeps stray resistance and inductance low. the dual sense pins allow for a full kelvin connection. make sure that sense + and sense C are isolated and connect close to the sense resistor. peak current occurs at 100mv of sense voltage v sense . so the nominal sense resistor is v sense /i pk . for example, a peak switch current of 10a requires a nominal sense resistor of 0.010 < note that the instantaneous peak power in the sense resistor is 1w, and that it is rated accordingly. the use of parallel resistors can help achieve low resistance, low parasitic inductance and increased power capability. size r sense using worst-case conditions, minimum l p , v sense and maximum v in . continuing the example, let us assume that our worst-case conditions yield an i pk of 40% above nominal, so i pk = 2.3a. if there is a 10% tolerance on r sense and minimum v sense = 88mv, then r sense t 110% = 88mv/2.3a and nominal r sense = 35m < . round to the nearest available lower value, 33m < . ltc4278 29 4278fc applications information selecting the load compensation resistor the expression for r cmp was derived in the operation section as: r cmp = k1 ? r sense ? 1 C dc ( ) esr + r ds(on) ? r1 ? n sf continuing the example: k1= v out v in ? eff ? ? ? ? ? ? = 5 48 ? 90% = 0.116 dc= 1 1+ n ? v in(nom) v out = 1 1 + 1 8 ? 48 5 = 45.5% if esr + r ds(on) = 8m r cmp = 0.116 ? 33m ? 1 ? 0.455 ( ) 8m ? 37.4k ? 1 3 = 3.25k this value for r cmp is a good starting point, but empirical methods are required for producing the best results. this is because several of the required input variables are diffcult to estimate precisely. for instance, the esr term above includes that of the transformer secondary, but its effective esr value depends on high frequency behavior, not simply dc winding resistance. similarly, k1 appears as a simple ratio of v in to v out times effciency, but theoretically estimating effciency is not a simple calculation. the suggested empirical method is as follows: 1. build a prototype of the desired supply including the actual secondary components. 2. temporarily ground the c cmp pin to disable the load compensation function. measure output voltage while sweeping output current over the expected range. approximate the voltage variation as a straight line. v out / i out = r s(out) . 3. calculate a value for the k1 constant based on v in , v out and the measured effciency. 4. compute: r cmp = k1 ? r sense r s(out) ? r1 ? n sf 5. verify this result by connecting a resistor of this value from the r cmp pin to ground. 6. disconnect the ground short to c cmp and connect a 0.1f flter capacitor to ground. measure the output imped - ance r s(out) = v out / i out with the new compensation in place. r s(out) should have decreased signifcantly. fine tuning is accomplished experimentally by slightly altering r cmp . a revised estimate for r cmp is: r cmp = r cmp ? 1 + r s(out)cmp r s(out) ? ? ? ? ? ? ? ? where r cmp is the new value for the load compensation resistor. r s(out)cmp is the output impedance with r cmp in place and r s(out) is the output impedance with no load compensation (from step 2). setting frequency the switching frequency of the ltc4278 is set by an external capacitor connected between the osc pin and ground. recommended values are between 200pf and 33pf, yielding switching frequencies between 50khz and 250khz. figure 12 shows the nominal relationship between external capacitance and switching frequency. place the capacitor as close as possible to the ic and minimize osc c osc (pf) 30 50 f osc (khz) 100 200 300 100 200 4278 f12 figure 12. f osc vs osc capacitor values ltc4278 30 4278fc applications information trace length and area to minimize stray capacitance and potential noise pick-up. you can synchronize the oscillator frequency to an external frequency. this is done with a signal on the sync pin. set the ltc4278 frequency 10% slower than the desired external frequency using the osc pin capacitor, then use a pulse on the sync pin of amplitude greater than 2v and with the desired frequency. the rising edge of the sync signal initiates an osc capacitor discharge forcing primary mosfet off (pg voltage goes low). if the oscillator frequency is much different from the sync frequency, problems may occur with slope compensation and system stability. also, keep the sync pulse width greater than 500ns. selecting timing resistors there are three internal one-shot times that are programmed by external application resistors: minimum on-time, enable delay time and primary mosfet turn-on delay. these are all part of the isolated fyback control technique, and their functions are previously outlined in the theory of operation section. the following information should help in selecting and/or optimizing these timing values. minimum output switch on-time (t on(min) ) minimum on-time is the programmable period during which current limit is blanked (ignored) after the turn-on of the primary-side switch. this improves regulator performance by eliminating false tripping on the leading edge spike in the switch, especially at light loads. this spike is due to both the gate/source charging current and the discharge of drain capacitance. the isolated fyback sensing requires a pulse to sense the output. minimum on-time ensures that the output switch is always on a minimum time and that there is always a signal to close the loop. the ltc4278 does not employ cycle skipping at light loads. therefore, minimum on-time along with synchronous rectifcation sets the switch over to forced continuous mode operation. the t on(min) resistor is set with the following equation r ton(min) k w ( ) = t on(min) ns ( ) ? 104 1.063 keep r ton(min) greater than 70k. a good starting value is 160k. enable delay time (endly) enable delay time provides a programmable delay between turn-off of the primary gate drive node and the subsequent enabling of the feedback amplifer. as discussed earlier, this delay allows the feedback amplifer to ignore the leakage inductance voltage spike on the primary side. the worst- case leakage spike pulse width is at maximum load condi - tions. so, set the enable delay time at these conditions. while the typical applications for this part use forced continuous operation, it is conceivable that a secondary- side controller might cause discontinuous operation at light loads. under such conditions, the amount of energy stored in the transformer is small. the fyback waveform becomes lazy and some time elapses before it indicates the actual secondary output voltage. the enable delay time should be made long enough to ignore the irrelevant portion of the fyback waveform at light loads. even though the ltc4278 has a robust gate drive, the gate transition time slows with very large mosfets. increase delay time as required when using such mosfets. the enable delay resistor is set with the following equation: r endly k w ( ) = t endly ns ( ) ? 30 2.616 keep r endly greater than 40k. a good starting point is 56k. primary gate delay time (pgdly) primary gate delay is the programmable time from the turn-off of the synchronous mosfet to the turn-on of the primary-side mosfet. correct setting eliminates overlap ltc4278 31 4278fc between the primary-side switch and secondary-side syn - chronous switch(es) and the subsequent current spike in the transformer. this spike will cause additional component stress and a loss in regulator effciency. the primary gate delay resistor is set with the following equation: r pgdly k w ( ) = t pgdly ns ( ) + 47 9.01 a good starting point is 15k. soft-start function the ltc4278 contains an optional soft-start function that is enabled by connecting an external capacitor between the sfst pin and ground. internal circuitry prevents the control voltage at the v cmp pin from exceeding that on the sfst pin. there is an initial pull-up circuit to quickly bring the sfst voltage to approximately 0.8v. from there it charges to approximately 2.8v with a 20a current source. the sfst node is discharged to 0.8v when a fault occurs. a fault occurs when the current sense voltage is greater than 200mv or the ics thermal (overtemperature) shut - down is tripped. when sfst discharges, the v cmp node voltage is also pulled low to below the minimum current voltage. once discharged and the fault removed, the sfst charges up again. in this manner, switch currents are reduced and the stresses in the converter are reduced during fault conditions. the time it takes to fully charge soft-start is: t ss = c sfst ? 1.4v 20 a = 70k w ? c sfst f ( ) switchers uvlo pin function the uvlo pin provides a user programming undervoltage lockout. this is typically used to provide undervoltage lockout based on v in . the gate drivers are disabled when uvlo is below the 1.24v uvlo threshold. an external resistive divider between the input supply and ground is used to set the turn-on voltage. the bias current on this pin depends on the pin volt- age and uvlo state. the change provides the user with adjustable uvlo hysteresis. when the pin rises above the uvlo threshold a small current is sourced out of the pin, increasing the voltage on the pin. as the pin voltage drops below this threshold, the current is stopped, further dropping the voltage on uvlo. in this manner, hysteresis is produced. referring to figure 13, the voltage hysteresis at v in is equal to the change in bias current times r a . the design procedure is to select the desired v in referred voltage hysteresis, v uvhys . then: r a = v uvhys i uvlo where: i uvlo = i uvlol C i uvloh is approximately 3.4a r b is then selected with the desired turn-on voltage: r b = r a v in(on) v uvlo ? 1 ? ? ? ? ? ? applications information v in r a ltc4278 (13a) uv turning on uvlo i uvlo r b v in r a ltc4278 (13b) uv turning off (13c) uv filtering uvlo uvlo r b v in r a2 r a1 c uvlo r b 4278 f13 i uvlo figure 13. uvlo pin function and recommended filtering ltc4278 32 4278fc applications information if we wanted a v in -referred trip point of 36v, with 1.8v (5%) of hysteresis (on at 36v, off at 34.2v): r a = 1.8v 3.4 a = 529k, use 523k r b = 523k 36v 1.23v ? 1 ? ? ? ? ? ? = 18.5k, use 18.7 k even with good board layout, board noise may cause problems with uvlo. you can flter the divider but keep large capacitance off the uvlo node because it will slow the hysteresis produced from the change in bias current. figure 13c shows an alternate method of fltering by split - ting the r a resistor with the capacitor. the split should put more of the resistance on the uvlo side. converter start-up the standard topology for the ltc4278 uses a third trans - former winding on the primary side that provides both the feedback information and local v cc power for the ltc4278 (figure 14). this power bootstrapping improves converter effciency but is not inherently self-starting. start-up is affected with an external preregulator circuit that condi - tions the input line voltage for the ltc4278 during start-up. upon application of power, c vcc is charged via the pre- regulator, thereby providing an appropriate supply voltage at the v cc pin for the ltc4278. this supply voltage is typically in the range 7v and is used during start-up. after converter startup, the third transformer winding becomes energized and is designed to generate a higher voltage than the preregulator. the higher voltage of the third winding turns off qpr and provides an effcient method to power the ltc4278. design of the v cc power circuitry involves selecting ap - propriate voltage ranges for both the preregulator and the third transformer winding. the preregulator voltage is set as low as possible while ensuring its worst-case minimum voltage is high enough to drive the switching fets gates during the startup period. the third winding output voltage is selected to ensure that its worst-case minimum voltage exceeds the preregulator voltage in order to turn off q pr . if the two voltage ranges overlap, the only disadvantage is that a small degradation in effciency may occur. it is also necessary to verify that the worst-case maximum winding voltage is not high enough to damage the b-e junction of q pr . control loop compensation loop frequency compensation is performed by connect - ing a capacitor network from the output of the feedback amplifer (v cmp pin) to ground as shown in figure 15. because of the sampling behavior of the feedback amplifer, compensation is different from traditional current mode controllers. normally only c vcmp is required. r vcmp can be used to add a zero, but the phase margin improvement traditionally offered by this extra resistor is usually already accomplished by the nonzero secondary circuit impedance. c vcmp2 can be used to add an additional high frequency pole and is usually sized at 0.1 times c vcmp . 17 r vcmp v cmp c vcmp 4278 f15 c vcmp2 figure 15. v cmp compensation network figure 14. typical power bootstrapping 4278 f14 v in v cc c vcc q pr ltc4278 pg fb gnd ? ? ? ltc4278 33 4278fc in further contrast to traditional current mode switch - ers, v cmp pin ripple is generally not an issue with the ltc4269 - 1. the dynamic nature of the clamped feedback amplifer forms an effective track/hold type response, whereby the v cmp voltage changes during the fyback pulse, but is then held during the subsequent switch-on portion of the next cycle. this action naturally holds the v cmp voltage stable during the current comparator sense action (current mode switching). application note 19 provides a method for empirically tweaking frequency compensation. basically, it involves introducing a load current step and monitoring the response. slope compensation the ltc4278 incorporates current slope compensation. slope compensation is required to ensure current loop stability when the dc is greater than 50%. in some switching regulators, slope compensation reduces the maximum peak current at higher duty cycles. the ltc4278 eliminates this problem by having circuitry that compensates for the slope compensation so that maximum current sense voltage is constant across all duty cycles. minimum load considerations at light loads, the ltc4278 derived regulator goes into forced continuous conduction mode. the primary-side switch always turns on for a short time as set by the t on(min) resistor. if this produces more power than the load requires, power will fow back into the primary dur - ing the off period when the synchronization switch is on. this does not produce any inherently adverse problems, although light load effciency is reduced. maximum load considerations the current mode control uses the v cmp node voltage and amplifed sense resistor voltage as inputs to the current comparator. when the amplifed sense voltage exceeds the v cmp node voltage, the primary-side switch is turned off. in normal use, the peak switch current increases while fb is below the internal reference. this continues until v cmp reaches its 2.56v clamp. at clamp, the primary-side mosfet will turn off at the rated 100mv v sense level. this repeats on the next cycle. it is possible for the peak primary switch currents as referred across r sense to exceed the max 100mv rating because of the minimum switch on time blanking. if the voltage on v sense exceeds 205mv after the minimum turn-on time, the sfst capacitor is discharged, causing the discharge of the v cmp capacitor. this then reduces the peak current on the next cycle and will reduce overall stress in the primary switch. short-circuit conditions loss of current limit is possible under certain conditions such as an output short-circuit. if the duty cycle exhibited by the minimum on-time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current is not controlled at the nominal value. it ratchets up cycle-by-cycle to some higher level. expressed mathematically, the requirement to maintain short-circuit control is: dc min = t on(min) ? f osc < i sc ? r sec + r ds(on) ( ) v in ? n sp where: t on(min) is the primary-side switch minimum on-time i sc is the short-circuit output current n sp is the secondary-to-primary turns ratio (n sec /n pri ) (other variables as previously defned) trouble is typically encountered only in applications with a relatively high product of input voltage times secondary to primary turns ratio and/or a relatively long minimum switch on time. additionally, several real world effects such as transformer leakage inductance, ac winding losses and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. prudent applications information ltc4278 34 4278fc design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction. output voltage error sources the ltc4278s feedback sensing introduces additional minor sources of errors. the following is a summary list: ? the internal bandgap voltage reference sets the reference voltage for the feedback amplifer. the specifcations detail its variation. ? the external feedback resistive divider ratio directly affects regulated voltage. use 1% components. ? leakage inductance on the transformer secondary reduces the effective secondary-to-feedback winding turns ratio (ns/nf) from its ideal value. this increases the output voltage target by a similar percentage. since secondary leakage inductance is constant from part to part (within a tolerance) adjust the feedback resistor ratio to compensate. ? the transformer secondary current fows through the impedances of the winding resistance, synchronous mosfet r ds(on) and output capacitor esr. the dc equivalent current for these errors is higher than the load current because conduction occurs only during the converters off-time. so, divide the load current by (1 C dc). if the output load current is relatively constant, the feedback resistive divider is used to compensate for these losses. otherwise, use the ltc4278 load compensation circuitry (see load compensation). if multiple output windings are used, the fyback winding will have a signal that represents an amalgamation of all these windings impedances. take care that you examine worst-case loading conditions when tweaking the voltages. power mosfet selection the power mosfets are selected primarily on the criteria of on-resistance r ds(on) , input capacitance, drain-to - source breakdown voltage (bv dss ), maximum gate voltage (v gs ) and maximum drain current (id (max) ). for the primary-side power mosfet, the peak current is: i pk(pri) = p in v in(min) ? dc max ? 1 + x min 2 ? ? ? ? ? ? applications information where x min is peak-to-peak current ratio as defned earlier. for each secondary-side power mosfet, the peak cur- rent is: i pk(sec) = i out 1 ? dc max ? 1 + x min 2 ? ? ? ? ? ? select a primary-side power mosfet with a bvdss greater than: bv dss i pk l lkg c p + v in(max) + v out(max) n sp where nsp refects the turns ratio of that secondary-to primary winding. llkg is the primary-side leakage induc - tance and cp is the primary-side capacitance (mostly from the drain capacitance (coss) of the primary-side power mosfet). a clamp may be added to reduce the leakage inductance as discussed. for each secondary-side power mosfet, the bv dss should be greater than: bv dss v out + v in(max) ? n sp choose the primary-side mosfet r ds(on) at the nominal gate drive voltage (7.5v). the secondary-side mosfet gate drive voltage depends on the gate drive method. primary-side power mosfet rms current is given by: i rms(pri) = p in v in(min) dc max for each secondary-side power mosfet rms current is given by: i rms(sec) = i out 1? dc max calculate mosfet power dissipation next. because the primary-side power mosfet operates at high v ds , a transition power loss term is included for accuracy. c miller is the most critical parameter in determining the transition loss, but is not directly specifed on the data sheets. ltc4278 35 4278fc applications information c miller is calculated from the gate charge curve included on most mosfet data sheets (figure 16). the secondary-side power mosfets typically operate at substantially lower v ds , so you can neglect transition losses. the dissipation is calculated using: p dis(sec) = i rms(sec) 2 ? r ds(on) (1 + d) with power dissipation known, the mosfets junction temperatures are obtained from the equation: t j = t a + p dis ? ja where t a is the ambient temperature and ja is the mosfet junction to ambient thermal resistance. once you have t j iterate your calculations recomputing d and power dissipations until convergence. gate drive node consideration the pg and sg gate drivers are strong drives to minimize gate drive rise and fall times. this improves effciency, but the high frequency components of these signals can cause problems. keep the traces short and wide to reduce parasitic inductance. the parasitic inductance creates an lc tank with the mosfet gate capacitance. in less than ideal layouts, a series resistance of 5 or more may help to dampen the ringing at the expense of slightly slower rise and fall times and poorer effciency. the ltc4278 gate drives will clamp the max gate voltage to roughly 7.5v, so you can safely use mosfets with maximum v gs of 10v and larger. synchronous gate drive there are several different ways to drive the synchronous gate mosfet. full converter isolation requires the synchro - nous gate drive to be isolated. this is usually accomplished by way of a pulse transformer. usually the pulse driver is used to drive a buffer on the secondary, as shown in the application on the front page of this data sheet. however, other schemes are possible. there are gate drivers and secondary-side synchronous controllers available that provide the buffer function as well as additional features. q a v gs a b 4278 f16 q b miller effect gate charge (q g ) figure 16. gate charge curve the fat portion of the curve is the result of the miller (gate to-drain) capacitance as the drain voltage drops. the miller capacitance is computed as: c miller = q b ? q a v ds the curve is done for a given v ds . the miller capacitance for different v ds voltages are estimated by multiplying the computed c miller by the ratio of the application v ds to the curve specifed v ds . with c miller determined, calculate the primary-side power mosfet power dissipation: p d(pri) = i rms(pri) 2 ? r ds(on) 1 + ( ) + v in(max) ? p in(max) dc min ? r dr ? c miller v gate(max) ? v th ? f osc where: r dr is the gate driver resistance (10) v th is the mosfet gate threshold voltage f osc is the operating frequency v gate(max) = 7.5v for this part (1 + d) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve. if you dont have a curve, use d = 0.005/c ? t for low voltage mosfets. ltc4278 36 4278fc applications information capacitor selection in a fyback converter, the input and output current fows in pulses, placing severe demands on the input and output flter capacitors. the input and output flter capacitors are selected based on rms current ratings and ripple voltage. select an input capacitor with a ripple current rating greater than: i rms(pri) = p in v in(min) 1? dc max dc max continuing the example: i rms(pri) = 29.5w 41v 1? 49.4% 49.4% = 0.728a keep input capacitor series resistance (esr) and inductance (esl) small, as they affect electromagnetic interference suppression. in some instances, high esr can also produce stability problems because fyback converters exhibit a negative input resistance characteristic. refer to application note 19 for more information. the output capacitor is sized to handle the ripple current and to ensure acceptable output voltage ripple. the output capacitor should have an rms current rating greater than: i rms(sec) = i out dc max 1? dc max continuing the example: i rms(sec) = 5.3a 49.4% 1? 49.4% = 5.24a this is calculated for each output in a multiple winding application. esr and esl along with bulk capacitance directly affect the output voltage ripple. the waveforms for a typical fyback converter are illustrated in figure 17. the maximum acceptable ripple voltage (expressed as a percentage of the output voltage) is used to establish a starting point for the capacitor values. for the purpose of simplicity, we will choose 2% for the maximum output output voltage ripple waveform secondary current primary current i pri ?v cout 4278 f17 ringing due to esl i pri n ?v esr figure 17. typical flyback converter waveforms ripple, divided equally between the esr step and the charging/discharging v. this percentage ripple changes, depending on the requirements of the application. you can modify the following equations. for a 1% contribution to the total ripple voltage, the esr of the output capacitor is determined by: esr cout 1% ? v out ? 1? dc max ( ) i out the other 1% is due to the bulk c component, so use: c out i out 1% ? v out ? f osc in many applications, the output capacitor is created from multiple capacitors to achieve desired voltage ripple, reliability and cost goals. for example, a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor satisfes the required bulk c. continuing our example, the output capacitor needs: esr cout 1% ? 5v ? 1? 49.4% ( ) 5.3a = 4m ? c out 5.3a 1% ? 5 ? 200khz = 600 f these electrical characteristics require paralleling several low esr capacitors possibly of mixed type. ltc4278 37 4278fc one way to reduce cost and improve output ripple is to use a simple lc flter. figure 18 shows an example of the flter. applications information unidirectional 58v transient voltage suppressor be installed between the diode bridge and the ltc4278 (d3 in figure 2). isolation the 802.3 standard requires ethernet ports to be electrically isolated from all other conductors that are user accessible. this includes the metal chassis, other connectors and any auxiliary power connection. for pds, there are two common methods to meet the isolation requirement. if there will be any user accessible connection to the pd, then an isolated dc/dc converter is necessary to meet the isolation requirements. if user connections can be avoided, then it is possible to meet the safety requirement by completely enclosing the pd in an insulated housing. in all pd applications, there should be no user accessible electrical connections to the ltc4278 or support circuitry other than the rj-45 port. layout considerations for the ltc4278 the ltc4278s pd front end is relatively immune to layout problems. excessive parasitic capacitance on the r class pin should be avoided. include a pcb heat sink to which the exposed pad on the bottom of the package can be soldered. this heat sink should be electrically connected to gnd. for optimum thermal performance, make the heat sink as large as possible. voltages in a pd can be as large as 57v for poe applications, so high voltage layout techniques should be employed. the shdn pin should be separated from other high voltage pins, like v portp , v neg , to avoid the possibility of leakage currents shutting down the ltc4278. if not used, tie shdn to v portn . the load capacitor connected between v portp and v neg of the ltc4278 can store signifcant energy when fully charged. the design of a pd must ensure that this energy is not inadvertently dissipated in the ltc4278. the polarity- protection diodes prevent an accidental short on the cable from causing damage. however if, v portn is shorted to v portp inside the pd while capacitor c1 is charged, r load c out2 1f v out c out 470f c1 47f 3 from secondary winding l1, 0.1h 4278 f18 + + figure 18. the design of the flter is beyond the scope of this data sheet. however, as a starting point, use these general guidelines. start with a c out 1/4 the size of the nonflter solution. make c1 1/4 of c out to make the second flter pole independent of c out . c1 may be best implemented with multiple ceramic capacitors. make l1 smaller than the output inductance of the transformer. in general, a 0.1h flter inductor is suffcient. add a small ceramic capacitor (c out2 ) for high frequency noise on v out . for those interested in more details refer to second-stage lc filter design, ridley, switching power magazine, july 2000 p8-10. circuit simulation is a way to optimize output capacitance and flters, just make sure to include the component parasitic. ltc switchercad ? is a terrifc free circuit simulation tool that is available at www.linear.com. final optimization of output ripple must be done on a dedicated pc b oard. parasitic inductance due to poor layout can signifcantly impact ripple. refer to the pc board layout section for more details. electro static discharge and surge protection the ltc4278 is specifed to operate with an absolute maximum voltage of C100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world (primarily v portn and v portp ) can routinely see peak voltages in excess of 10kv. to protect the ltc4278, it is highly recommended that the smaj58a ltc4278 38 4278fc current will fow through the parasitic body diode of the internal mosfet and may cause permanent damage to the ltc4278. in order to minimize switching noise and improve output load regulation, connect the gnd pin of the ltc4278 directly to the ground terminal of the v cc decoupling capacitor, the bottom terminal of the current sense resistor and the ground terminal of the input capacitor, using a ground plane with multiple vias. place the v cc capacitor immediately adjacent to the v cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate drive currents. use a low esr ceramic capacitor. take care in pcb layout to keep the traces that conduct high switching currents short, wide and with minimal overall loop area. these are typically the traces associated with the switches. this reduces the parasitic inductance and also minimizes magnetic feld radiation. figure 19 outlines the critical paths. keep electric feld radiation low by minimizing the length and area of traces (keep stray capacitances low). the drain of the primary-side mosfet is the worst offender in this category. always use a ground plane under the switcher circuitry to prevent coupling between pcb planes. check that the maximum bv dss ratings of the mosfets are not exceeded due to inductive ringing. this is done by viewing the mosfet node voltages with an oscilloscope. if it is breaking down, either choose a higher voltage device, add a snubber or specify an avalanche-rated mosfet. place the small-signal components away from high frequency switching nodes. this allows the use of a pseudo-kelvin connection for the signal ground, where high di/dt gate driver currents fow out of the ic ground pin in one direction (to the bottom plate of the v cc decoupling capacitor) and small-signal currents fow in the other direction. keep the trace from the feedback divider tap to the fb pin short to preclude inadvertent pick-up. for applications with multiple switching power converters connected to the same input supply, make sure that the input flter capacitor for the ltc4278 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple which could interfere with the ltc4278 operation. a few inches of pc trace or wire (l @ 100nh) between the c in of the ltc4278 and the actual source v in , is suffcient to prevent current sharing problems. applications information t2 t1 c r c vin ms mp gate turn-on gate turn-on r sense ? ? c vcc sg v cc pg v cc v cc v cc v in gate turn-off gate turn-off q4 q3 c out 4278 f19 out ? ? ? + + + figure 19. layout critical high current paths ltc4278 39 4278fc typical application ? ? 4.7nf, 2kv ps2801-1-l 1 3 6 4 30.9 294k 0.1f 100v 54.9k 3.01k 12k 100k 1.82k 38.3k 12m 100 5.1 1f 2.2nf 33pf 0.1f 33nf 1nf epa4271ge cmlt3820g 10k l1 180nh hat2169h epc3472g-lf cmlt7820g bat54 t on sync pgdly uvlo pwrgd /pwrgd sense ? v cmp sense + r cmp v neg v neg r class shdn v portp v portn v portn gnd osc endly ltc4278idkd exposed pad solder side fb nc v cc sg pg c cmp 20k 7.5v cmhz4693 l2 8.2h v cc 1f 20 bas21 + 10f 100v c6 c2 3.3f 2 4278 ta02 pds5100h smaj58a 21.5k 10 24k aux ? aux + auxiliary supply 8v to 57v vport_n vport_p b1100 (8 plcs) b1100 spare2 spare1 l1: coilcraft, do1813p-181hc l2: wrth, 7443330820 c2, c6: tdk, c3225x7s2a335m c1, c3: murata, grm31cr60j226ke19 c9: tdk, c3225x5r0j107m rxct txct 20k 2.49k s1b 47 220pf 4 3 1 2 5 v cc 6 12 11 7 8 10k fdms86101 3.3k 3.3nf 10k 15 1f +v out +v out 5v at 4.5a ?v out ? ? c3, c1 22f 2 c9 100f t2p t2p bss63lt1 fmmt624 ? ltc4278 40 4278fc package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. note: 1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) bottom view?exposed pad r = 0.115 typ 0.20 0.05 1 16 17 32 6.00 ref 6.43 0.10 2.65 0.10 4.00 0.10 0.75 0.05 0.00 ? 0.05 0.200 ref 7.00 0.10 (dkd32) qfn 0707 rev a 0.40 bsc recommended solder pad layout apply solder mask to areas that are not soldered 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer 6.43 0.05 2.65 0.05 0.70 0.05 0.40 bsc 6.00 ref 3.10 0.05 4.50 0.05 0.40 0.10 0.20 0.05 package outline r = 0.05 typ dkd package 32-lead plastic dfn (7mm 4mm) (reference ltc dwg # 05-08-1734 rev a) note: 1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) bottom view?exposed pad r = 0.115 typ 0.20 0.05 1 16 17 32 6.00 ref 6.43 0.10 2.65 0.10 4.00 0.10 0.75 0.05 0.00 ? 0.05 0.200 ref 7.00 0.10 (dkd32) qfn 0707 rev a 0.40 bsc recommended solder pad layout apply solder mask to areas that are not soldered 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer 6.43 0.05 2.65 0.05 0.70 0.05 0.40 bsc 6.00 ref 3.10 0.05 4.50 0.05 0.40 0.10 0.20 0.05 package outline r = 0.05 typ dkd package 32-lead plastic dfn (7mm 4mm) (reference ltc dwg # 05-08-1734 rev a) ltc4278 41 4278fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 3/12 added b1100 to schematic revised max junction temperature added typical application 1, 19 2 39 c 4/12 updated component values on typical application updated maximum junction temperature to 125c updated typical application 1 2 39 (revision history begins at rev b) ltc4278 42 4278fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com ? linear technology corporation 2009 lt 0412 rev c ? printed in usa related parts part number description comments lt ? 1952 single switch synchronous forward counter synchronous controller, programmable volt-sec clamp, low start current ltc3803-3 current mode flyback dc/dc controller in thinsot tm 300khz constant-frequency, adjustable slope compensation, optimized for high input voltage applications ltc3805 adjustable frequency current mode flyback controller slope comp, overcurrent protect, internal/external clock ltc3825 isolated no-opto synchronous flyback controller with wide input supply range adjustable switching frequency, programmable undervoltage lockout, accurate regulation without trim, synchronous for high effciency ltc4257-1 ieee 802.3af pd interface controller 100v 400ma internal switch, programmable classifcation, dual current limit ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only, ieee-compliant pd detection and classifcation, autonomous operation or i 2 c control ltc4259a-1 quad ieee 802.3af power over ethernet controller ac or dc disconnect, ieee-compliant pd detection and classifcation, autonomous operation ltc4263 single ieee 802.3af power over ethernet controller ac or dc disconnect, ieee-compliant pd detection and classifcation, autonomous operation or i 2 c control ltc4263-1 high power single pse controller internal switch, autonomous operation, 30w ltc4264 high power pd interface controller with 750ma current limit 750ma internal switch, programmable classifcation current to 75ma, precision dual current limit with disable. ltc4265 ieee 802.3at high power pd interface controller with 2-event classifcation 2-event classifcation recognition, 100ma inrush current, single-class programming resistor, full compliance to 802.3at ltc4266 ieee 802.3at quad pse controller supports ieee 802.3at type 1 and type 2 pds, 0.34 channel resistance, advanced power management, high reliability 4-point pd detection, legacy capacitance detect ltc4267-1 ieee 802.3af pd interface with an integrated switching regulator 100v 400ma internal switch, programmable classifcation, 200khz constant-frequency pwm, optimized for ieee-compliant pd system ltc4267-3 ieee 802.3af pd interface with an integrated switching regulator 100v 400ma internal switch, programmable classifcation, 300khz constant-frequency pwm, optimized for ieee-compliant pd system ltc4269-1 ieee 802.3af/ieee 802.3at pd with synchronous no-opto flyback controller 2-event classifcation recognition, 92% power supply effciency, flexible aux support, superior emi ltc4269-2 ieee 802.3af/ieee 802.3at pd with synchronous forward controller 2-event classifcation recognition, 94% power supply effciency, flexible aux support, superior emi |
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